
include config.mak

help:
	@echo "\033[32mRTL-AUTOMATA RTL Automatic Build Script Usage:\033[0m"
	@echo "\033[33melaborate\033[0m to examine given TOP_MODULE and generate \033[34mhierarchy.rpt\033[0m"
	@echo "\033[33mlint\033[0m to check syntax errors of RTLs listed in \033[34mhierarchy.rpt\033[0m"
	@echo "\033[33mvlint\033[0m to strictly check syntax errors in \033[34mhierarchy.rpt\033[0m using verilator"
	@echo "\033[33mautosim\033[0m to automaically simulate testebench of the given \033[34mTB_MODULE\033[0m"
	@echo "\033[33mysyx_build\033[0m to automaically perform recursive difftest of the given \033[34mTB_MODULE\033[0m and \033[34mMANUAL_INCFILE\033[0m"
	@echo "\033[33mfpgaflow_VENDOR\033[0m to synthesize the project and attempt to generate bitstream(\033[31mNOT PRESENT\033[0m)"
	@echo "\033[32mATTENTION:Replace VENDOR with specific vendor name (gowin/anlogic/altera)\033[0m"
	@echo "\033[33masicflow\033[0m to run RTL2GDS digital ASIC flow(\033[31mNOT PRESENT\033[0m)"
	@echo "\033[33mclean\033[0m to clean all objects and temp files"
$(OBJ_DIR):
	mkdir -p $(OBJ_DIR)
$(HIERARCHY_FILE): $(OBJ_DIR)
	make elaborate
elaborate: $(OBJ_DIR)
	bash ./script/elaborate.sh $(TOP_MODULE) $(RTL_DIR) $(INCLUDE_DIR) $(HIERARCHY_FILE)
lint:$(HIERARCHY_FILE)
	bash ./script/lint.sh $(INCLUDE_DIR) $(HIERARCHY_FILE)
vlint:
	rm -rf $(OBJ_DIR)/shadowed_src
	mkdir $(OBJ_DIR)/shadowed_src
	bash ./script/shadowed_src.sh $(HIERARCHY_FILE) $(OBJ_DIR)/shadowed_src/ >/dev/null
	verilator --lint-only -Wall -I$(OBJ_DIR)/shadowed_src -I$(RTL_DIR) $(TOP_MODULE) &>$(OBJ_DIR)/vlint.log

simprep:
	bash ./script/autosim.sh $(TB_MODULE) $(TB_DIR) $(SIMU_INCDIR) $(REPORT_DIR)/tb_hierarchy.rpt $(RTL_DIR) $(OBJ_DIR)
	bash ./temp/PREPROCESSOR.sh
autosim:
	$(MAKE) simprep
	cat $(REPORT_DIR)/tb_hierarchy.rpt|xargs iverilog -g2005-sv -o $(OBJ_DIR)/tb.run $(SIMU_PARAM)
	vvp $(OBJ_DIR)/tb.run
	@echo "\033[32mSeems Simulation Finished,\033[33m make wave \033[32mto show waveform\033[0m"
vsim:
	rm -rd $(OBJ_DIR)/shadowed_src
	mkdir $(OBJ_DIR)/shadowed_src
	-ln -s $(OBJ_DIR)/shadowed_src $(YSYX_DIR)/projects/$(PROJECT_NAME)/vsrc
	-ln -s $(OBJ_DIR)/shadowed_src $(YSYX_DIR)/projects/$(PROJECT_NAME)/build
	bash ./script/shadowed_src.sh $(REPORT_DIR)/tb_hierarchy.rpt $(OBJ_DIR)/shadowed_src/ >/dev/null
	cd $(YSYX_DIR) && ./build.sh -b -e vostok564 -t $(TB_MODULE).v -s -w

wave:
	gtkwave $(OBJ_DIR)/$(TB_MODULE).vcd

fpgaflow_%:$(HIERARCHY_FILE)

asicflow:#$(HIERARCHY_FILE)
	bash ./script/hierarchy_export.sh 
	qflow gui -T $(ASIC_PDK) -p temp $(TOP_MODULE)

simtopgen:$(REPORT_DIR)/tb_hierarchy.rpt
	bash ./script/hierarchy_export.sh ./temp/testsuite.v $(REPORT_DIR)/tb_hierarchy.rpt

#ctools:
#	$(MAKE) -C sim/make#rm -r $(REPORT_DIR)/*

.PHONY: make help

.PHONY: clean
clean:
	
	-rm -rf $(OBJ_DIR)
	-find ./ -name "*.bak"|xargs rm
	-find ./ -name "*.log"|xargs rm
	-find ./ -name "*.area"|xargs rm


YSYX_DIR=../oscpu-framework
PROJECT_NAME=vostok564
TEST_BINARY=coremark-riscv64-mycpu
RECURSIVE_DIR="."
BUILD_PARAM=-e $(PROJECT_NAME) -d -b -s -a "-i $(TEST_BINARY).bin -b 0" -m "EMU_TRACE=1 WITH_DRAMSIM3=1" #
YDBG_PARAM=-e $(PROJECT_NAME) -d -b -s -a "-i $(TEST_BINARY).bin --dump-wave -b 0" -m "EMU_TRACE=1 WITH_DRAMSIM3=1" -w #
BUILD_PARAM_NODRAM=-e $(PROJECT_NAME) -d -b -s -a "-i $(TEST_BINARY).bin -b 0" -m "EMU_TRACE=1" #
YDBG_PARAM_NODRAM=-e $(PROJECT_NAME) -d -b -s -a "-i $(TEST_BINARY).bin --dump-wave -b 0" -m "EMU_TRACE=1" -w #
RECURSIVE_PARAM= -e $(PROJECT_NAME) -b -r $(RECURSIVE_DIR)
RECUR_AXI_PARAM= -e $(PROJECT_NAME) -b -r "non-output/cpu-tests non-output/riscv-tests" -m "WITH_DRAMSIM3=1"
 #ATTENTION: Due to iverilog can't recognize DPI-C functions, these listed files needs to be manually 
MANUAL_INCFILE=$(TB_DIR)/DIFFTEST.INC

ysyx_prep:
	-rm -rd $(OBJ_DIR)/shadowed_src
	mkdir $(OBJ_DIR)/shadowed_src
	-ln -s $(OBJ_DIR)/shadowed_src $(YSYX_DIR)/projects/$(PROJECT_NAME)/vsrc
	cat $(MANUAL_INCFILE) >$(OBJ_DIR)/runfile.lst
	ln $(SIMTOP) $(YSYX_DIR)/projects/$(PROJECT_NAME)/vsrc/SimTop.v
	bash ./script/shadowed_src.sh $(OBJ_DIR)/runfile.lst $(OBJ_DIR)/shadowed_src/ 
	bash ./script/hierarchy_export.sh ./temp/shadowed_src/$(TOP_MODULE).v $(HIERARCHY_FILE)
	-rm -rf $(YSYX_DIR)/projects/$(PROJECT_NAME)/build
	cp -f ./makefile_ysyxproj $(YSYX_DIR)/projects/$(PROJECT_NAME)/makefile

ysyx_prep_KRNL:
	$(MAKE) elaborate TOP_MODULE=PRV564_Kernel
	$(MAKE) ysyx_prep MANUAL_INCFILE=$(TB_DIR)/DIFFTEST_KRNL.INC SIMTOP=$(TB_DIR)/SimTop_KRNL.v TOP_MODULE=PRV564_Kernel

ysyx_prep_FIB:
	$(MAKE) elaborate TOP_MODULE=PRV564_top
	$(MAKE) ysyx_prep MANUAL_INCFILE=$(TB_DIR)/DIFFTEST_FIB.INC SIMTOP=$(TB_DIR)/SimTop_FIB.v TOP_MODULE=PRV564_top

ysyx_prep_AXI:
	$(MAKE) elaborate TOP_MODULE=Vostok564_top
	$(MAKE) ysyx_prep MANUAL_INCFILE=$(TB_DIR)/DIFFTEST_AXI.INC SIMTOP=$(TB_DIR)/SimTop_AXI.v TOP_MODULE=Vostok564_top

ysyx_build_KRNL:
	$(MAKE) ysyx_prep_KRNL
	cd $(YSYX_DIR) && bash ./build.sh $(BUILD_PARAM_NODRAM)
ysyx_recursive_KRNL:
	$(MAKE) ysyx_prep_KRNL
	-cp -Rf  $(BINARY_CASE)/*.bin  $(YSYX_DIR)/bin/
	cd $(YSYX_DIR) && bash ./build.sh $(RECURSIVE_PARAM)
ysyx_debug_KRNL:
	$(MAKE) ysyx_prep_KRNL
	cd $(YSYX_DIR) && bash ./build.sh $(YDBG_PARAM_NODRAM)

ysyx_build_FIB:
	$(MAKE) ysyx_prep_FIB
	cd $(YSYX_DIR) && bash ./build.sh $(BUILD_PARAM_NODRAM)
ysyx_recursive_FIB:
	$(MAKE) ysyx_prep_FIB
	-cp -Rf  $(BINARY_CASE)/*.bin  $(YSYX_DIR)/bin/
	cd $(YSYX_DIR) && bash ./build.sh $(RECURSIVE_PARAM)
ysyx_debug_FIB:
	$(MAKE) ysyx_prep_FIB
	cd $(YSYX_DIR) && bash ./build.sh $(YDBG_PARAM_NODRAM)

ysyx_build_AXI:
	$(MAKE) ysyx_prep_AXI
	cd $(YSYX_DIR) && bash ./build.sh $(BUILD_PARAM)
ysyx_recursive_AXI:
	$(MAKE) ysyx_prep_AXI
	-cp -Rf  $(BINARY_CASE)/*.bin  $(YSYX_DIR)/bin/
	cd $(YSYX_DIR) && bash ./build.sh $(RECUR_AXI_PARAM)
ysyx_debug_AXI:
	$(MAKE) ysyx_prep_AXI
	cd $(YSYX_DIR) && bash ./build.sh $(YDBG_PARAM)
YOSYS_OPT=o3
ysyx_finaldbg:
	$(MAKE) ysyx_xport
	-mkdir -p ./temp/shadowed_src
	bash ./script/hierarchy_export.sh ./temp/shadowed_src/$(TOP_MODULE).v $(HIERARCHY_FILE)
	-rm $(YSYX_DIR)/projects/soc/vsrc/*
	#yosys -s yosys_$(YOSYS_OPT).tcl 
	ln ./temp/shadowed_src/$(TOP_MODULE).v $(YSYX_DIR)/projects/soc/vsrc/$(TOP_MODULE).v 
	#ln ./temp/ysyx_$(YOSYS_OPT).v $(YSYX_DIR)/projects/soc/vsrc/$(TOP_MODULE).v 
	ln ./RTL/PRV564Config.v $(YSYX_DIR)/projects/soc/vsrc 
	ln ./RTL/PRV564Define.v $(YSYX_DIR)/projects/soc/vsrc 
	cd  $(YSYX_DIR) && bash ./build.sh -e soc -b -s -y -v '--timescale "1ns/1ns" -Wno-fatal --trace' -a "-i ysyxSoC/loader/rtthread-loader.bin" #
	#rtthread --dump-wave

ysyx_xport:
	$(MAKE) elaborate lint
	bash ./script/hierarchy_export.sh ./temp/$(TOP_MODULE)_rtl.v $(HIERARCHY_FILE)
	cat ./RTL/PRV564Define.v >./temp/$(TOP_MODULE).v
	echo '\n'>>./temp/$(TOP_MODULE).v
	cat ./RTL/PRV564Config.v >>./temp/$(TOP_MODULE).v
	echo '\n'>>./temp/$(TOP_MODULE).v
	cat  ./temp/$(TOP_MODULE)_rtl.v >>./temp/$(TOP_MODULE).v
	-bash ./POSTPROCESS.sh ./temp/$(TOP_MODULE).v
	
ysyx_submit:
	$(MAKE) ysyx_xport
	rm -f $(YSYX_DIR)/projects/soc/vsrc/$(TOP_MODULE).v
	#yosys -s yosys_$(YOSYS_OPT).tcl 
	#cp -f ./temp/ysyx_$(YOSYS_OPT).v $(YSYX_DIR)/projects/soc/vsrc/$(TOP_MODULE).v 
	cp -f ./temp/$(TOP_MODULE).v $(YSYX_DIR)/projects/soc/vsrc 
	-verilator -Wall --lint-only -I$(YSYX_DIR) $(YSYX_DIR)/projects/soc/vsrc/ysyx_210152.v
	cd $(YSYX_DIR) && bash submit.sh
